1. Field of the Invention
The present invention relates to a memory control device for controlling an access to a dynamic random access memory (hereinafter called a DRAM) in an information processing apparatus employing a virtual memory system.
2. Description of the Related Art
A virtual memory is a technique of seemingly enlarging capacity of a RAM. That is, where the virtual memory is used, capacity of a RAM that a programmer can use becomes larger than that of a physically existing RAM. In the virtual memory systems a virtual memory area is produced by dividing a program in segments or page units, and transferring the segments or page units between a main memory and a secondary memory. However, segments or page units of a program are not always allocated to continuous areas in actual allocation. Therefore, mapping of an address (logical address) used in the program on an address (physical address) where the program is actually allocated to the main memory is necessary. This mapping mechanism is realized by a memory management unit (MMU). The MMU generally uses a translation look-aside buffer (hereinafter called a TLB) to perform the mapping at a high speed.
A method of accessing a DRAM in a system using a DRAM as the main memory and translating further the physical address translated from the logical address by a TLB to a DRAM address will be explained. The basic access method to the DRAM is to select a row of data first by a row address, and then to select an object data among the row of data by a column address. The TLB is connected to the DRAM through a multiplexer which time shares the physical address from the TLB to generate the row address and column address of the DRAM.
As a method of accessing the DRAM at a high speed there is a method of access in a fast page mode. The fast page mode is the mode to access the DRAM only supplying a column address at the following access in sequentially access of the row data of the same column address. FIG. 1 is a block diagram showing a memory control device described in, for example, the Japanese Patent Application Laid-Open No. 4-38694 (1982). The memory control device is assumed to be connected to a DRAM with 1M-bit, to translate a 24-bit logical address to a 20-bit physical address, and further to translate the physical address to a DRAM address.
In FIG. 1, numeral 1 designates a TLB for translating a logical page number A.sub.N 23-A.sub.N 16 among a logical address A.sub.N 23-A.sub.N 0 to a physical page number A'.sub.N 19-A'.sub.N 16; numeral 2 designates a multiplexer for generating both a row address A'.sub.N 19-A'.sub.N 16/A.sub.N 15-A.sub.N 10 and a column address A.sub.N 9-A.sub.N 0 of the DRAM by time sharing on receipt of both the physical page number A'.sub.N 19-A'.sub.N 16 translated by the TLB and an address in a logical page A.sub.N 15-A.sub.N 0 (which becomes an address in a physical page without translation) among the logical address A.sub.N 23-A.sub.N 0; and numeral 3 designates a latch for latching the row address A'.sub.N 19-A'.sub.N 16/A.sub.N 15-A.sub.N 10 on receipt of the same time shared in the multiplexer 2, the latch 3 comprising a latch 3a for latching the high order 4 bits A'.sub.N 19-A'.sub.N 16 of a row address and a latch 3b for latching the low order 6 bits A.sub.N 15-A.sub.N 10 of a row address.
Numeral 4 designates a comparator for comparing a row address A'.sub.N 19-A'.sub.N 16 with a row address A'.sub.N-1 19-A'.sub.N-1 16 on receiving both the high order 4 bits of a row address A'.sub.N 19-A'.sub.N 16 among the row address outputted by the multiplexer 2 and the output of the latch 3a latching the row address A'.sub.N-1 19-A'.sub.N-1 16 at the last access to output a comparing result signal 5; numeral 6 designates a comparator for comparing a logical address A.sub.N 15-A.sub.N 10 with a row address A.sub.N-1 15-A.sub.N-1 10 on receiving both the logical address (row address) A.sub.N 15-A.sub.N 10 and the output of the latch 3b latching the logical address (row address) A.sub.N-1 15-A.sub.N-1 10 at the last access to output a comparing result signal 7; and numeral 8 designates a RAS (Row Address Strobe)/CAS (Column Address Strobe) generation circuit for generating a RAS signal to control a row address reading timing and a CAS signal to control a column address reading timing on receiving both the comparing result signal 5 from the comparator 4 and the comparing result signal 7 from the comparator 8. The multiplexer 2 together with the RAS/CAS generation circuit are taken as a DRAM access control unit.
FIG. 2 is a diagram showing a method of translating a logical address to a physical address and then the physical address to a DRAM address where, for example, a 1M-bit DRAM is used. The logical address is composed of a logical page number representing a page of a divided program and an address in a logical page. The logical page numbers are allocated to a secondary memory (such as a magnetic disk) and a main memory (DRAM), so that the logical page number is larger than the number of actual pages in the main memory. Generally, an address in a logical page is used as an address in a physical page without translation. The physical address thus obtained is divided into the row address and column address of the DRAM.
The operation of the memory control device having such construction as above will be explained hereinafter. First, high order 8 bits A.sub.N 23-A.sub.N 18 of a logical address among a 24-bit logical address A.sub.N 23-A.sub.N 0 are inputted into a TLB 1, which in turn translates the logical address A.sub.N 23-A.sub.N 16 to a 4-bit physical address A'.sub.N 19-A'.sub.N 16 to output. Low order 16 bits A.sub.N 15-A.sub.N 0 of a logical address among the logical address A.sub.N 23-A.sub.N 0 are unnecessary to be translated, so that they are used in that state as a physical address A.sub.N 15-A.sub.N 0. The multiplexer 2 receives a 20-bit physical address A'.sub.N 19-A'.sub.N 16/A.sub.N 15-A.sub.N 0 and outputs a 10-bit row address A'.sub.N 19-A'.sub.N 16/A.sub.N 15-A.sub.N 10 and a 10-bit column address A.sub.N 9-A.sub.N 0 in synchronism with a strobe signal generated by the RAS/CAS generation circuit 8.
The latch 3a latches the high order 4 bits A'.sub.N 19-A'.sub.N 16 of the row address outputted from the multiplexer 2, while the latch 3b latches the low order 6 bits A.sub.N 15-A.sub.N 10 of the row address outputted from the multiplexer 2. The comparator 4 receives both the row address A'.sub.N-1 19-A'.sub.N-1 16 at the last access outputted from the latch 3a and the row address A'.sub.N 19-A'.sub.N 16 outputted from the multiplexer 2, and compares the both. When these two addresses agree, the comparator 4 makes the comparing result signal 5 active, but when these two addresses disagree, the comparator 4 makes the comparing result signal 5 inactive. On the other hand, the comparator 6 receives both the row addresses A.sub.N-1 15-A.sub.N-1 10 at the last access outputted from the latch 3b and the logical addresses A.sub.N 15-A.sub.N 10, and compares whether these two addresses are identical with each other. When these two addresses are identical with each other, the comparator 6 makes the comparing result signal 7 active, while the comparator 8 makes the comparing result signal 7 inactive when these two addresses are not identical with each other.
The RAS/CAS generation circuit 8 receives the comparing result signal 5 and the comparing result signal 7 from the comparator 4 and the comparator 6, respectively, and if both the comparing result signal 5 and the comparing result signal 7 are active, generates a RAS/CAS signal for performing a DRAM access in a fast page mode. On the other hand, if at least either of the comparing result signal 5 and the comparing result signal 7 is inactive, the circuit 8 generates a RAS/CAS signal for performing a DRAM access in a normal mode of a basic access.
Since the conventional memory control device is configured as above, the device has a problem that whether the access in the fast page mode to the DRAM being able is not judged at a high speed when the comparison result signal 7 from the comparator 6 is active because the access mode to the DRAM is decided upon the comparison result signal 5 from the comparator 4, though the access mode to the DRAM is judged at a high speed when the comparison result signal 7 from the comparator 6 is inactive because the access mode to the DRAM is decided irrespective of the comparison result signal 5. That is, the address inputted into the comparator 4 must be a physical address, so that in order to obtain the physical address, a logical address must be translated by the TLB 1 to the physical address. In other words, this translating time prevents the judgment from being performed at a high speed.